With workbench working to some degree (see earlier blog entries), I am in the mood for a bit of refactoring.
I am going to rework the cpu core. As a start I wrote some code on devpac to attempt to measure the cycle timings of various instructions. To do this, I used the VHPOS register and basically recorded it as I ran the instruction MOVE.W $6(a0),(a1)+. That gave me a difference between each consecutive address of 8. According to the documentation 1 pulse of the VHPOS register is 280ns so in theory that means the cost of MOVE.W $6(a0),(a1)+ is 8*280ns.
Next i inserted a NOP into the proceedings, this gave me 10*280ns. So in theory the NOP takes 2*280ns. This all seems quite logical. So what about for instance MOVE.W #1000,d0, well same process and that gives us 12 which removing the cost of the move gives me 4*280ns.
My overall intention is to break the cpu down below the instruction level. So for instance :
MOVE.W #1000,d0
becomes :
or something along those lines. Not a trivial task, but it feels like the right way to go to emulate the behaviour of the odd/even bus allocation on the amiga hardware. A resolution of 280ns is fine, since at least at present thats the fastest event in the emulation. Having said that EXG d5,d6 gives a count of 11 (which is 3*280ns), not a problem so long as i don't find anything smaller than 1.
For the interested :
jsr START
rts
START
lea $dff000,a0
move.w #$0100,$96(a0) ; disable dma and interrupts
move.w #$4000,$9A(a0) ; to ensure no bus contention
lea DATA,a1
wait
move.w $06(a0),d0
and.w #$FF00,d0
bne wait ; just so i start at a fixed point
move.w $06(a0),d0
REPT 1000
move.w #1000,d7
move.w $06(a0),(a1)+
ENDR
move.w $06(a0),d1
move.w #$8100,$96(a0) ; re-enable interrupts so i can continue
move.w #$C000,$9A(a0) ;to use devpac
rts
DATA ds.w 1000
Written by Savoury SnaX, 27 Aug 2009